All stock codes associated to this product
KHX28C12T2K2/8X, 740617225761
KHX28C12T2K2/8X
8GB (4GB 512M x 64-Bit x 2 pcs.)
DDR3-2800 CL12 240-Pin DIMM Kit
DESCRIPTION
Kingston's KHX28C12T2K2/8X is a kit of two 512M x 64-bit (4GB) DDR3-2800 CL12 SDRAM (Synchronous DRAM), 1Rx8 memory modules, based on eight 512M x 8-bit FBGA compo-nents per module. Each module kit supports Intel XMP (Extreme Memory Profiles). Total kit capacity is 8GB. Each module kit has been tested to run at DDR3-2800 at a low latency timing of 12-14-14 at 1.65V. The SPDs are pro-grammed to JEDEC standard latency DDR3-1600 timing of 11-11-11 at 1.5V. Each 240-pin DIMM uses gold contact fingers. The JEDEC standard electrical and mechanical specifi-cations are as follows:
FEATURES
- JEDEC standard 1.5V (1.425V ~ 1.575V) Power Supply
- VDDQ = 1.5V (1.425V ~ 1.575V)
- 800MHz fCK for 1600Mb/sec/pin
- 8 independent internal bank
- Programmable CAS Latency: 11, 10, 9, 8, 7, 6
- Programmable Additive Latency: 0, CL - 2, or CL - 1 clock
- 8-bit pre-fetch
- Burst Length: 8 (Interleave without any limit, sequential with starting address 000 only), 4 with tCCD = 4 which does not allow seamless read or write [either on the fly using A12 or MRS]
- Bi-directional Differential Data Strobe
- Internal(self) calibration : Internal self calibration through ZQ pin (RZQ : 240 ohm 1%)
- On Die Termination using ODT pin
- Average Refresh Period 7.8us at lower than TCASE 85C,3.9us at 85C < TCASE < 95C
- Asynchronous Reset
- PCB : Height 2.122 (53.90mm) w/ heatsink, single sided componen
XMP TIMING PARAMETERS
- JEDEC: DDR3-1600 CL11-11-11 @1.5V
- XMP Profile #1: D3-2800 CL12-14-14 @1.65V
- XMP Profile #2: D3-2666 CL11-13-13 @1.65V
- SPECIFICATIONS
- CL(IDD) 11 cycles
- Row Cycle Time (tRCmin) 48.125ns (min.)
- Refresh to Active/Refresh 260ns (min.)
- Command Time (tRFCmin)
- Row Active Time (tRASmin) 35ns (min.)
- Maximum Operating Power 2.160 W* (per module)
- UL Rating 94 V - 0
- Operating Temperature 0oC to 85oC
- Storage Temperature -55oC to +100oC
Power will vary depending on the SDRAM used
